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6 00 ma , 6 mhz , synchronous step - down dc - to - dc converter adp2121 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2011 analog devices, inc. all rights reserved. features p eak efficiency : 92% o perating f requency : 6 mhz typical quiescent current in auto mode: 36 a f ixed o utput v oltage : 1.8 v, 1. 82 v, 1.85 v, 1.875 v, 2.3 v maximum guaranteed load current: 600 ma at v in = 2.7 v to 5.5 v input v oltage : 2.3 v to 5.5 v t ypical shutdown supply current : 0.3 a automatic power - saving mode compatible with tiny multilayer inductors internal synchronous rectifier internal compensation internal soft start output to ground short - circuit protection cycle - by - cycle c urrent - limit protection enable/shutdown logic input undervoltage lockout thermal shutdown protection ultra small 6 - ball , 0.4 mm pitch, 1.17 mm 2 wlcsp applications mobile phones digital cameras digital audio portable equipment general description the adp2121 is a high frequency, low quiescent current step - down dc - to - dc converter optimized for portable applications in which board area and battery life are critical constraints. the 6 mhz operating frequency enables the use of tiny ceramic induc - tors and capacitors. addit ionall y, the synchronous rectification improves efficiency and results in few er external components. at high load current s , th e device use s a voltage regulating pulse - width modulation (pwm) mode that maintains a constant frequency with excellent stability and transient response. in forced pwm mode, the converter continue s operati ng in pwm for light loads. at light load conditions in auto mode, the adp2121 can automatically enter a power - saving mode that uses pulse - frequency modulation (pfm) to reduce the e ffective switching frequency and ensure the longest battery life in portable applications. during logic controlled shutdown ( en 0.4 v), the input is disconnected from the output and draws less than 0. 3 a current (typical) from the source. typical appl ication circuit vin 07407-001 gnd mode en fb sw c in 2.2f c out 4.7f adp2121 l 0.47h on o ff pwm auto b2 c1 a2 c2 a1 b1 output v oltage 1.8v, 1.82v, 1.85v, 1.875v, 2.3v input voltage* 2.3v to 5.5v *for output voltage = 2.3 v, input voltage = 2.9 v to 5.5v. figure 1. typical performance 07407-062 55 0.1 1 10 100 1000 65 75 85 95 load current (ma) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v auto mode v in = 2.7 v (v in = 2.9v for v out = 2.3v) efficienc y (%) figure 2 . efficiency vs. load current for each voltage option the adp2121 has an input voltage range of 2.3 v to 5.5 v (2.9 v to 5.5 v for v out = 2.3 v), allowing the use of a single li+/l i ? polymer cell, 3 - cell alkaline or ni - mh cell, and other standard power sources. the converter can source up to 600 ma and is internally compensated to minimize external components. other key features, such as cycle - by - cycle peak current limit, soft start , undervoltage lockout (uvlo), output - to - ground short - circuit protection, and thermal shutdown, protect the internal and external circuit components. table 1 . output voltage options input voltage range (v) typical start - up time ( s) fixed output voltage (v) 2.3 to 5.5 75 1.8, 1.85, 1.875 2.3 to 5.5 275 1.82 2.9 to 5.5 100 2.3
adp2121 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ap plications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 typical performance ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absol ute maximum ratings ............................................................ 4 thermal data ................................................................................ 4 thermal resistance ...................................................................... 4 esd ca ution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 14 overview ..................................................................................... 14 mode selection ........................................................................... 14 enable/shutdown ....................................................................... 15 internal control features .......................................................... 15 applications information .............................................................. 17 inductor selection ...................................................................... 17 input capacitor selection .......................................................... 17 output capacitor selection ....................................................... 17 pcb layout guidelines .................................................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 1/11 rev. a to rev. b changes to table 2 summary .......................................................... 3 changes to undervoltage lockout threshold parameter and output voltage accuracy parameter in table 2 ........................... 3 6/ 10 rev. 0 to rev. a changes to features, general description, figure 1, and figure 2 ; added table 1 ; renumbered sequentially ................ 1 changes to table 2 ............................................................................ 3 change s to table 3 ............................................................................ 4 change to typical performance characteristics condition statement ; reorganized typical performance characteristics section; changes to figure 4 , figure 6, figure 7, and figure 9 ; added figure 5 and figure 8; renumbered sequentially ....... 6 changes to figure 10 to figure 12 ; added figure 13 to figure 15 ... 7 changes to figure 16 , figure 17, figure 19, and figure 20 .......... 8 changes to figure 2 2; added figure 23 and figu re 24 ................ 9 added figure 40, figure 42, figure 43, and figure 45 .............. 12 added figure 46 and figure 48; changes to figure 47 ............. 13 changes to figure 51 and the overview section ....................... 14 changes to the auto mode (pfm and pwm switching) section, figure 53, the mode transitio n section, and the enable/ shutdown section ....................................................................... 15 changes to the output short - circuit protection section and figure 55 ...................................................................................... 16 changes to the output capacitor selection section ................. 17 changes to table 6 , table 7, and table 8 ..................................... 18 changes to ordering guide .......................................................... 20 4 /0 9r ev i sion 0 : initial versi on
adp2121 rev. b | page 3 of 20 specifications v in = en = 3.6 v; v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, and 2.3 v; t ypical values are at t a = 25c ; and minimum/maximum limits guaranteed for t j = ? 40 c to + 125 c, 1 table 2 . unless otherwise noted. parameters conditions min typ max unit supply input voltage range v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v 2.3 5.5 v v out = 2.3 v 2.9 5.5 v quiescent current a uto mode , no load, not switching, t a = ?40c to 85c 36 56 a pwm mode , no l oad 10 ma shutdown current v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v en = 0 v , t a = ?40c to 85c 0. 3 1 a v out = 2.3 v, v en = 0 v, t a = ?40c to 85c 0.4 1 .5 a undervoltage lockout undervoltage lockout threshold v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v in rising 2.1 2.3 v v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v in falling 1.6 2.0 v v out = 2.3 v, v in rising 2.4 2.6 v v out = 2.3 v, v in falling 1.9 2.3 v output maximum continuous output current 2 v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v in = 2.3 v 300 ma v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v in = 2.5 v 500 ma v out = 1.8 v, 1.82 v, 1.85 v, 1.875 v, v in = 2.7 v to 5.5 v 600 ma v out = 2.3 v, v in = 2.9 v to 5.5 v 600 ma output voltage accuracy 3 auto mode, v in = 3.6 v, t a = 25c, no load, with respect to v out ?3 +3 % pwm mode, v in = 2.5 v to 4.5 v, no load, with respect to v out ?3 +3 % load regulation 4 pwm mode, i load = 1 ma to 600 ma ?0. 2 %/a feedback bias current v out = 1.8 v, v fb = 1.8 v and v out = 1.82 v, v fb = 1.82 v 3.8 8 a v out = 1.85, v fb = 1.85 v and v out = 1.875 v, v fb = 1.875 v 4.1 8 a v out = 2.3 v , v fb = 2.3 v 6 .4 8 a switching characteristics sw on resistance (r dson ) p- channel switch 220 440 m n- channel synchronous rectifier 260 5 50 m sw leakage current v in = 5.5 v, v sw = 0 v and 5.5 v 5 a sw current limit p- channel switch, open loop, t a = ?40c to 125c 790 1000 1222 ma p- channel switch, open loop, t a = ?40c to 85c 828 1000 1222 ma oscillator frequency 5.36 6 6.64 mhz en/mode input logic v in = 2.3 v to 5.5 v high threshold voltage 1.3 v low threshold voltage 0.4 v leakage current v in = v en = v mode = 5.5 v 0.01 1 a soft start time from en 1.2 v to stable v out soft start period 5 v out = 1.82 v, r loa d = 5.1 275 310 s v out = 1.8 v, 1.85 v, 1.875 v , r load = 5.1 75 85 s v out = 2.3 v , r load = 5.1 100 115 s short - circuit threshold 1.24 v thermal shutdown thermal shutdown threshold 150 c thermal shutdown hysteresis 15 c 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc); typical values are at t a = 25c. 2 guaranteed by design. the maximum output current guarantee for 2.3 v to 2.5 v increases linearly from 300 ma to 500 ma. the maximum output current guarantee for 2.5 v to 2.7 v increases linearly from 500 ma to 600 ma. for greater than 2.7 v, the maximum output current guarantee is 600 ma. 3 transients not included in voltage accuracy specifications. for pfm mode, the vout accuracy specification is for the upper point of the ripple. 4 the load regulation typical value includes all voltage options. the typical v alue is different for each voltage option, but can be up to ?0.2 %/a. 5 typical value characterized on bench. maximum specification guaranteed by design. c in = 2.2 f (grm155r60j225m), l = 0.47 h ( lqm2hpnr47mg0l), c out = 4.7 f ( grm155r60j475me87d ).
adp2121 rev. b | page 4 of 20 absolute maximum rat ings table 3. parameter rating vin to gnd ? 0.3 v to +6 v en , mode to gnd ? 0.3 v to v in fb , sw to gnd ? 0.3 v to vin + 0.2 v operating ambient temperature range (i load 600 ma ) C 40c to +85c operating jun ction temperature range C 40c to + 125c storage temperature C 45c to +150c soldering conditions jedec j - std -020 esd ( electrostatic discharge) human body model 4 kv stresses above those listed under absolute maximum ratings may cause permanent da mage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the ad p2121 can be damaged when the junction temperature limits are exceeded. monitoring ambient tempera - ture does not guaran tee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor pcb thermal resistance, the maximum ambient temperature may need to be derated. in applications with moderate power diss ipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature ( t a ), the power dissipation of the device (p d ), and the junction - to - ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the following formula: t j = t a + ( p d ja ) the junction - to - ambient t hermal resistance ( ja ) of the package is based on modeling and calculation using a 2- and 4- layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipati on exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. refer to jedec jesd51 - 9 for detailed information about board construction. thermal resistance the junction - to - ambient thermal resistance of the system ( ja ) is specified for worst - case conditions, that is, a device soldered in a circuit boa rd for surface - mount packages. table 4 . package type ja unit 6- ball wlcsp 2- layer b oard 198 c/w 4- layer board 105 c/w esd caution
adp2121 rev. b | page 5 of 20 pin configuration and function descripti ons mode vin sw fb gnd top view (bal l side down) (bumps on opposite side) not to scale 07407-003 1 a b c 2 bal l a1 indic at or en figure 3 . pin configuration table 5 . pin function descriptions pin no. mnemonic description a1 mod e mode select. this pin toggles between auto mode (pfm and pwm switching) and pwm mode . set mode low to allow the part to operate in auto mode. pull mode high to force the part to operate in pwm mode. the voltage applied to mode should never be h igher than the voltage applied to vin. do not leave this pin floating. b1 sw switch node. c1 fb feedback divider input. connect the output capacitor from fb to gnd as close as possible to the adp2121 to set the output voltage ripple and to complete the control loo p. a2 vin power supply input. connect the input capacitor from vin to gnd as close as possible to the adp2121. b2 en enable. pull this pin high to enable the part. set this pin low to disable the part. do not leave this pin floating. c2 gnd ground pin .
adp2121 rev. b | page 6 of 20 typical performance characteristics v in = 3.6 v, v out = 1.82 v, l = 0.47 h ( 1800 ma, 1008 , lqm2hpnr47mg0l ), c in = 2.2 f (6.3 v, 0402 , x5r , grm155r60j225m), c out = 4.7 f (6.3 v, 0402, x5r , gr m155r60j475me87d ), en = v in , and t a = 25c, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 1000 load current (ma) efficiency (%) 07407-004 au t o mode pwm mode v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.0v v out = 1.82v figure 4. efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 load current (ma) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v pwm mode auto mode efficiency (%) 07407-049 figure 5 . efficiency vs. load current for all output voltages 100 90 80 70 60 50 40 30 20 0.1 1 10 100 1000 load current (ma) efficiency (%) 07407-016 au t o mode pwm mode l = 0.47h 1008 l = 0.47h 0805 l = 0.45h 0603 v in = 2.7v v out = 1.82v figure 6 . efficiency vs. load current for various inductor sizes 100 90 80 70 60 50 40 30 20 10 0 2.3 3.1 2.7 3.9 3.5 4.7 4.3 5.5 5.1 input voltage (v) efficiency (%) 07407-007 i out = 300m a i out = 100m a i out = 10m a i out = 1m a v out = 1.82 v figure 7 . efficiency vs. input voltage (auto mode) 75 78 81 84 87 90 93 2.3 2. 7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 i nput vo lt age (v) efficienc y (%) i out = 100ma v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v 07407-050 figure 8 . efficiency vs. input voltage for all output voltages (auto mode) 100 95 90 85 80 75 70 65 60 55 50 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 in p ut voltage (v) efficiency (%) 07407-019 l = 0.47h 1008 l = 0.47h 0805 l = 0.45h 0603 au t o mode v in = 2.7v vout = 1.82v figure 9 . efficiency vs. input voltage for various inductor sizes
adp2121 rev. b | page 7 of 20 44 42 40 38 36 34 32 30 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) quiescent current (a) 07407-010 t a = ?40c t a = +85c t a = +25c v out = 1.82v figure 10 . auto mode quiescent current vs. input voltage over temperature (nonswitching, no load) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) shutdown current (a) 07407-011 t a = ?40c t a = +85c t a = +25c v out = 1.82v figure 11 . s hutdown current vs. input voltage over temperature 16 14 12 10 8 6 4 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) quiescent current (ma) 07407-013 t a = ?40c t a = +85c t a = +25c v out = 1.82v v out = 1.82v figure 12 . pwm mode quiescent current vs. input voltage over temperature (switching, no load) 30 32 34 36 38 40 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input vo lt age (v) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v quiescent current ( a ) 07407-051 figure 13 . auto mode quiescent current vs. input volt age for all voltage options (nonswitching, no load) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input vo lt age (v) shutdown current ( a) v out = 1.8v v out = 1. 82 v v out = 1.85v v out = 1.8 75 v v out = 2.3v 07407-052 figure 14 . shutdown current vs. input voltage for all voltage options 3 5 7 9 11 13 15 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 i nput vo lt age (v) quiescent current (ma) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v 07407-053 figure 15 . pwm mode quiescent current vs. input voltage for all voltage opt ions (switching, no load)
adp2121 rev. b | page 8 of 20 90 80 75 85 70 65 60 55 50 45 0.1 1 10 100 1000 load current (ma) efficiency (%) 07407-006 au t o mode v in = 3.6v v out = 1.82v t a = ?40c t a = +85c t a = +25c figure 16 . efficiency vs. load current over temperature 1.87 1.86 1.85 1.84 1.83 1.82 0.1 1 10 100 1000 load current (ma) output voltage (v) 07407-005 au t o mode v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.0v v out = 1.82v figure 17 . output voltage accuracy (auto mode) 360 340 320 300 280 260 240 220 200 180 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) n-channel r dson (m ?) 07407-015 t a = ?40c t a = +85c t a = +25c figure 18 . n - channel drain - source on re sistance 100 90 80 70 60 50 40 30 20 10 0 250 200 150 100 50 0 0.1 1 10 100 1000 load current (ma) efficiency (%) power loss (mw) 07407-009 efficienc y v out = 1.82 v power loss v in = 2.7v v in = 3.6v v in = 4.2v v in = 5.0v figure 19 . efficiency and power loss vs. load current (auto mode) 1.835 1.830 1.825 1.820 1.815 1 10 100 1000 load current (ma) output voltage (v) 07407-008 v in = 2.7v v in = 3.6v v in = 4.2v pwm mode v in = 5.0v v out = 1.82v figure 20 . output voltage accuracy (pwm mode) 400 350 300 250 200 150 100 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) p-channel r dson (m ?) 07407-012 t a = ?40c t a = +85c t a = +25c figure 21 . p - channel drain - source on resistance
adp2121 rev. b | page 9 of 20 180 160 140 120 100 80 60 40 20 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) auto mode switching threshold (ma) 07407-014 pwm oper a tion pfm oper a tion v out = 1.82v figure 22 . auto mode switching threshold vs. input voltage 1 10 120 130 140 150 160 170 180 190 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input vo lt age (v) au t o mode rising switching threshold (ma) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v pfm operation 07407-054 figure 23 . auto mode rising switching threshold vs. input voltage for all voltage options 40 60 80 100 120 140 160 180 200 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input vo lt age (v) auto mode falling switching threshold (ma) v out = 1.8v v out = 1.82v v out = 1.85v v out = 1.875v v out = 2.3v pwm operation 07407-055 figure 24 . auto mode falling switching threshold vs. input voltage for all voltage options 07407-022 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 25 . load transient response, 0 ma to 150 ma (v in = 2.5 v, auto mode) 07407-023 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 26 . load transient response, 0 ma to 150 ma (v in = 3.6 v, auto mode) 07407-024 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 27 . load transient response, 0 ma to 150 ma (v in = 4.5 v, auto mode)
adp2121 rev. b | page 10 of 20 07407-025 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 28 . load transient response, 0 ma to 150 ma (v in = 2.5 v, pwm mode) 07407-026 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 29 . load transient response, 0 ma to 150 ma (v in = 3.6 v, pwm mode) 07407-027 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 30 . load transient response, 0 ma to 150 ma (v in = 4.5 v, pwm mode) 07407-028 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 31 . load transient response, 50 ma to 250 ma (v in = 2.5 v, auto mode) 07407-029 time (20s/div) output voltage (50mv/div) load current (100ma/div) figure 32 . load transient response, 50 ma to 250 ma (v in = 3.6 v auto mode) 07407-030 time (20s/div) output voltage (50mv/div, 1.82v offset) load current (100ma/div) figure 33 . load transient response, 50 ma to 250 ma (v in = 4.5 v, auto mode)
adp2121 rev. b | page 11 of 20 07407-031 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figur e 34 . load transient response, 50 ma to 250 ma (v in = 2.5 v, pwm mode) 07407-032 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figure 35 . load transient response, 50 ma to 250 ma (v in = 3.6 v, pwm mode) 07407-033 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figure 36 . load transient response, 50 ma to 250 ma (v in = 4.5 v, pwm mode) 07407-034 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figure 37 . load transient response, 150 ma to 400 ma (v in = 2.5 v, pwm mode) 07407-035 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figure 38 . load transient response,150 ma to 400 ma (v in = 3.6 v, pwm m ode) 07407-036 time (20s/div) output voltage (50mv/div, 1.82v dc offset) load current (100ma/div) figure 39 . load transient response, 150 ma to 400 ma (v in = 4.5 v, pwm mode)
adp2121 rev. b | page 12 of 20 07407-056 time (10 s/div) en pin voltage (5v/div) v in = 3.6v v out = 1.8v no load output voltage (500mv/div) inductor current (200ma/div) figure 40 . start - up waveform, no load 07407-018 v in = 3.6v v out = 1.82v no load time (40s/div) output voltage (500mv/div) enable pin voltage (5v/div) inductor current (200ma/div) figure 41 . start - up waveform, no load time (10s/div) 07407-057 v in = 3.6v v out = 2.3v noload output voltage (500mv/div) inductor current (200ma/div) en pin voltage (5v/div) figure 42 . start - up waveform, no load time (10s/div) 07407-058 v in = 3.6v v out = 1.8v r load = 5.1 output voltage (500mv/div) inductor current (200ma/div) en pin voltage (5v/div) figure 43 . start - up waveform, heavy load 07407-021 v in = 3.6v v out = 1.82v r load = 5.1 ? time (40s/div) output voltage (500mv/div) enable pin voltage (5v/div) inductor current (200ma/div) figure 44 . start - up waveform, heavy load time (10s/div) 07407-059 v in = 3.6v v out = 2.3v r load = 5.1 output voltage (500mv/div) inductor current (200ma/div) en pin voltage (5v/div) figure 45 . start - up waveform, heavy load
adp2121 rev. b | page 13 of 20 time (200s/div) 07407-060 v in = 3.6v v out = 1.8v output voltage (200mv/div) inductor current (500ma/div) figure 46 . output short - circuit response time (1ms/div) 07407-037 output voltage (200mv/div) inductor current (500ma/div) v out = 1.82v figure 47 . output short - circuit response time (200s/div) 07407-061 v in = 3.6v v out = 2.3v output voltage (200mv/div) inductor current (500ma/div) figure 48 . output short - circuit response 07407-017 time (1s/div) output voltage (20mv/div, 1.82v dc offset) switch node voltage (2v/div) inductor current (200ma/div) v in = 3.6v v out = 1.82v i out = 25ma figure 49 . pfm mode operation 07407-020 time (100ns/div) output voltage (20mv/div, 1.82v dc offset) switch node voltage (1v/div) inductor current (200ma/div) v in = 3.6v v out = 1.82v i out = 200ma figure 50 . pwm mode operation
adp2121 rev. b | page 14 of 20 theory of operation pwm comp bandgap bg thermal shutdown soft start pgnd agnd threshold detect b1 c2 sw gnd v out 470nh a2 v bat 2.3v to 5.5v b2 en v in fb 07407-038 bg agnd c1 fb v out ref pfm agnd r1 r2 eamp pfm comparator threshold detect a1 mode logic and pwm/pfm control pfm detect shoot- through cont rol pref nref pilim zxcomp pv in vin av in 2.2f x5r 6.3v pdrive ndrive 4.7f x5r 6.3v 6mhz oscillator ramp v(v in ) compensation on o ff pwm auto figure 51 . internal block diagram o verview the adp2121 is a high efficiency, synchronous step - down dc - to - dc converter t hat provides up to 600 m a of continuous output current. it operates from a 2.3 v to 5.5 v input voltage for the 1.8 v, 1.82 v, 1.85 v, and 1.875 v (typical) fixed - output voltages , and from a 2.9 v to 5.5 v input voltage for the 2.3 v (typical) output volta ge . the 6 mhz operating frequency enables the use of tiny external components. the internal control schemes of the adp2121 give excellent stability and transient response. external con trol for mode selection and device enabl e provide power - saving options t hat are aided by internal features such as synchronous rectification and compen - sation . other i nternal f eatures , such as cycle - by - cycle peak curre nt limit, soft start, undervoltage lockout, output - to - ground short - circuit protection, and thermal shutdown , p rotect the internal and external circuit components. mode s election the adp 2121 has two modes of operation (pwm mode and auto mode) , determined by the state of the mode pin . pull the mode pin high to force the co nverter to operate in pwm mode regardless of the output current . otherwise, set mode low to allow the converter to automatically enter the power - saving pfm mode at light load currents . do not leave this pin floating. the mode pin is not designed for dynamic control and should not be changed after the adp2121 is enabled. p ulse -w idth m odulation (pwm) mode the pwm mode forces the par t to maintain a fixed frequency of 6 mhz (typical ) over all load conditions. the adp2121 uses a hybrid proprietary voltage mode control scheme to control the duty cycle o ver load current and line voltage variation. this control provides excellent stability, transient response , and output regulation but results in lower efficiencies at light load currents.
adp2121 rev. b | page 15 of 20 07407-039 time (100ns/div) output voltage (20mv/div, 1.82v dc offset) switch node voltage (1v/div) inductor current (200ma/div) v in = 3.6v v out = 1.82v i out = 200ma figure 52 . typical pwm operation auto mo de (pfm and pwm switching) auto mode is a power - saving feature that enables the converter to switch between pwm and pfm in response to the output load. auto mode is enabled when the mode pin is pulled low. in auto mode, t h e adp2121 operates in pfm mode fo r light load currents and switches to pwm mode for medium and heavy load currents . figure 53 uses the typical threshold values of the 1.82 v output voltage option to demonstrate the behavior of the adp2121 in auto mode. the thr eshold values will shift accordingly for other output voltages . 1.875v 1.820v 0m a output vo lt age (v) induc t or current (ma) time (s) time (s) mode transition point* i out = 70m a t o 170m a (typical) *pfm and pwm threshold v aries with input vo lt age. see figure 22, figure 23 and figure 24 for typica l v alues. 07407-040 figure 53 . pfm -to- pwm transition point , v out = 1.82 v p ulse frequency modulation (pfm) when the converter is operat ing under light load conditions , the effective sw itching frequency and supply current are decreased and varied using pfm to regulate the output voltage. this results in improved efficiencies and lower quiescent currents. in pfm mode, the converter only switches when necessary to keep the output voltage w ithin the pfm limits set by an internal compa rator (see figure 53 ). switching stops when the upper limit is reached and resumes when the lower limit is reached. when the upper level is reached, the output stage and oscillator tu rn off to reduce the quiescent current. during this stage, the output capacitor supplies the current to the load. as the output capacitor discharges and the output voltage reaches the lower pfm comparator threshold, switching resumes and the process repea ts. the output voltage, switching node voltage, and inductor current during this process are shown in figure 54 . 07407-041 time (1s/div) output voltage (20mv/div, 1.82v dc offset) switch node voltage (2v/div) inductor current (200ma/div) v in = 3.6v v out = 1.82v i out = 25ma figure 54 . typical pfm operation mode tr ansition when the mode pin is low, t he converter switches between pfm and pwm modes automatically to maintain optimal transient response and efficiency. the mode transition point depends on the input voltage. hysteresis exists in the transition point to prevent instability and decreased efficiencies that could result if the converter were able to oscillate between pfm and pwm for a fixed input voltage and load current. see figure 22, figure 23 , and figure 24 for typical va lues. a switch from pfm to pwm occurs when the output voltage dips below the nominal value of the output voltage option . switching to pwm allows the converter to maintain efficiency and supply a larger current to the load . the switch from pwm to pfm occurs when the output current is below the pfm threshold for multiple consecutive switching cycles. switching to pfm allows the converter to save power by supply ing the lighter load current with fewer switching cycles. figure 53 shows that the output voltage in pfm mode is slightly higher to keep the adp2121 from oscillating between modes , ensuring stable operation. e nable/s hutdown the en input turns the adp 2121 on or off. connect en to gnd or logic low to shut down the part and reduc e the current consumption to 1.0 a ( maximum ). connect en to vin or to logic high to enable the part . do not leave this pin floating. internal control fea tures overc urrent protection to ensure that excessively high currents do not damage the inductor, the adp2121 incorporates cycle - by - cycle overcurrent protection. this function is accomplished by monitoring the instantaneous peak current on the power pmos switch. if this current exceeds the maximum level (1 a typ ical ), the pmos is immediately turned off. th is minimizes the potential for damage to power components during certain faults and transient events. the value listed in table 2 is an open loop dc tested value. inherent
adp2121 rev. b | page 16 of 20 delays in the current - limit comparator allow a slight i ncrease and variation in this specification. so ft start to prevent excessive input inrush current at startup, the adp2121 operates with an internal soft start . when en goes high, or when the part recovers from a fault (uvlo, tsd, or short - circuit protecti on ), a soft start timer begins . the soft start timer cor - responds to the maximum soft start period for the given fixed output voltage. during this time, the peak current limit is gradually increased to its maximum. as seen in fig ure 40 through figure 45 , the output voltage passes through several stages to ensure that the converter is able to start up effectively and in proper sequence. after the soft start period has expired, the peak current limit rem ains at 1 a (typ ical ), and the part enters the operating mode determined by the mode pin . synchronous rectification in addition to the p - channel mosfet switch, the adp2121 includes an n - channel mosfet switch to build the synchronous rectifier. the synchro nous rectifier improves efficiency, especially for small load currents, and reduces cost and board space by eliminating the need for an external rectifier. compensation the control loop is internally compensated to deliver maxi - mum performance with no add itional external components . the adp2121 is designed to work with 0.47 h chip inductors and 4.7 f capacitors (see table 6 , table 7 , and table 8 .) other values may redu ce performance and/or stability. under v oltage lockout (uvlo) if the input voltage is below the uvlo threshold, the adp2121 automatically turns off the power switches and places the part into a low power consumption mode. this prevents potentially erratic o peration at low input voltages. the uvlo levels have approximately 100 mv of hystere sis to ensure glitch - free startup. output sh ort - circuit protection if the ou tput voltage is inadvertentl y shorted to gnd, a standar d dc - to - dc controller deliver s maximum p ower into that short. this may result in a potentially catastrophic failure. to pre ve nt this, the adp2121 senses when the output voltage is below the short - circuit protection threshold ( typ ically 1.24 v). at this point, the controller turns off for approx imately 1.8 ms (v out = 1.82 v), 0.44 ms (v out = 1.8 v and 1.85 v), or 0.48 ms (v out = 2.3 v) , and then automatically initiates a soft start s equence. this cycle repeat s until the short is removed or the part is disabled. this dramatically reduces the power delivered into the short circuit , yet still allows the converter to recover if the fault is removed. time (1ms/div) 07407-042 output voltage (200mv/div) inductor current (500ma/div) figure 55 . output short - circuit protection, v out = 1.82 v thermal shutdown (tsd) protection the adp2121 also includes tsd prot ection. if the die temperature exceeds 150 c (typical), the tsd protection activate s and turn s off the power devices. they remain off until the die temperature falls below 1 35 c (typical), at which point the converter restarts.
adp2121 rev. b | page 17 of 20 applications information the external component selection for the adp2121 applica - tions circuit is driven by the load requirement an d begins with the selection of the i nductor . after the inductor is chosen, c in and c out can be selected . components can b e identi fied using the selection guid e and recommended selection tables in this section. i nductor selection the high switching frequency of the adp2121 allows for minimal output voltage ripple, even with small inductors. inductor sizing is a trade - off betw een efficiency and transient response. a small inductor leads to a larger inductor current ripple , which provides better transient response but degrades efficiency. due to the high switching frequency of the adp2121, multilayer ceramic inductors can be use d for an overall smaller solution size. shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (emi). as a guideline, the peak - to - peak current ripple of the inductor is typically set to i l = 0.45 i load (1) where i load is the maximum output current. the largest ripple current, i l , occurs at the maximum input voltage. i t is important that the inductor be capable of handling the maximum peak inductor current, i pk , determined by the follo wing equation: i pk = i load(max) + i l /2 (2 ) the dc current rating of the inductor should be greater than the calculated i pk to prevent core saturation . the adp2121 is designed for application s with a 0.47 h inductor. other values are not recommended , and stable operation over all conditions is not guaranteed with their use. table 6 shows the available 0.47 h surface - mount inductors that have been tested with the adp2121. i nput capacitor selec tion the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. select an input capacitor capable of withstanding the rms input current for the maximum load curre nt in the application using the following equation: in out in out max out rms v vvv ii ) ( )( ? = (3) the input capacitor reduces the input voltage ripple caused by the switch currents on the vin pin. place the input capacitor as close as possible to the vin pin. in principle, different types of capacitors can be considered, but for battery - powered ap plications, the best choice is the multilayer ceramic capacitor, due to its small size and low equivalent series resistance (esr). table 7 offers suggestions for suitable input capacitor s. all capacitors listed in the table are multilayer ceramic capacitors. it is recommended that the vin pin be bypassed with a 2.2 f or larger ceramic input capacitor if the supply line has a distri - buted capacitance of at least 10 f. if not, then at least a 10 f capacitor is recommended on th e input supply pin. the input capacitor can be increased without any limit for better input voltage filtering. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended . y5u and z5u dielectrics are not recommended, due to their poor tem perature and dc bias characteristics. o utput capacitor sele ction the output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. for a given loop crossover frequency (the frequency at which the loop gain drops to 0 db), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. the adp2121 has been designed to op erate with small ceramic capaci tors in the 4.7 f to 10 f range that have low esr and equival ent series inductance (esl) . these components are able , therefore , to meet stringent output voltage ripple specifications. x5r or x7r dielectrics with a voltage rating o f 6. 3 v are recommended . table 8 shows a list of output ml cc capacitors recommended for adp2121 applications. the minimum effective capacitance required for stable operation is 1.5 f. w hen choosing output capacitors, it is also important to acco unt for the loss of capacitance due to output voltage dc bias. this may result in using a capacitor with a higher rated voltage to achieve the desired capacitance value. additionally, i f ceramic output capacitors are used, the capacitor rms ripple current rating should always meet the application requirements. the rms ripp le current is calculated as )( )( ) ( 32 1 )( maxin sw out maxin out rms vfl v vv i cout ? = (4 ) at nominal load currents, the converter operates in pulse frequency mode (pf m) , and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltag e ripple caused by charging and discharging the output capacitor. v out = i l ( esr + 1/(8 c out f sw )) (5 ) the largest voltage ripple occur s at the highest input voltage. at light load currents, if mode is set low, then the converter operates in the power - sav ing mode (pfm) , and the output voltage ripple increases .
adp2121 rev. b | page 18 of 20 table 6 . recommended inductor selection manufacturer series inductance (h) dcr ( m?) current rating (ma) size (l w h) (mm) package murata lqm2hpnr47mg0l 0.47 20% 40 25% 1800 2.5 0 2.0 0 0.90 1008 lqm21pnr47mc0d 0.47 20% 120 25% 1100 2.0 0 1.25 0.50 0805 taiyo yuden brc1608tr45m 0.45 20% 90 30% 800 1.6 0 0.8 0 0.8 0 0603 tdk mlz2012dr47m t 0.47 20% 180 30% 550 2.00 1.25 1.25 0805 glfr1608 t r47m -lr 0.47 20% 50 30% 475 1. 6 0.80 0.80 0603 ta ble 7 . recommended input capacitor selection manufacturer part number capacitance ( f) voltage rating (v) temperature coefficient size (l w h) (mm) package murata grm155r60j225m 2.2 6.3 x5r 1.0 0.5 0.5 0402 taiyo yuden jmk105bj225mv -f 2.2 6.3 x5r 1.0 0.5 0.5 0402 table 8 . recommended ou tput capacitor selection manufacturer part number capacitance ( f) voltage rating (v) temperature coefficient size (l w h) (mm) package murata grm188r60j475ke19d 4.7 6.3 x5r 1.6 0.8 0.8 0603 grm155r60j475me87d 4.7 6.3 x5r 1.0 0.5 0.5 0402 t aiyo yuden amk105bj475mv -f 4.7 4 x5r 1.0 0.5 0.5 0402
adp2121 rev. b | page 19 of 20 pcb layout guide lines 07407-043 vin mode adp2121 en cin gnd cout l1 sw vout 3.4mm 2.5mm figure 56 . solution size with a 1008 inductor 2.0mm 07407-044 vin mode adp2121 en cin gnd cout l1 sw vout 2.65mm figure 57 . solution size with a 0805 inductor 07407-045 1.8mm 2.2mm cout vin mode adp2121 en cin gnd l1 sw vout figure 58 . solution size with a 0603 inductor for high efficiency, good regulation, and stability with the adp2121 , a well -designed pcb is required. use the f ollow ing guidelines when d esigning pcbs : ? keep the low esr input capacitor, c in , close to vin and gnd. ? keep high current traces as short and as wide as possible. ? avoid routing high impedance traces near any node connected to sw or near the inductor to prevent radiated noise injection. ? keep the low esr output capacitor, cout, close to fb and gnd of t he adp2121. long trace lengths from the part to the output capacitor add series inductance and may cause instability or increased ripple.
adp2121 rev. b | page 20 of 20 outline dimensions 021908- a a 12 b c 0.400 bsc bal l pitch bot t om view (bal l side up) 0.940 0.900 0.860 1.340 1.300 1.260 top view (bal l side down) a1 bal l corner 0.660 0.600 0.540 0.430 0.400 0.370 0.280 0.260 0.240 0.230 0.200 0.170 0.075 nom coplanarity 0.800 bsc figure 59 . 6 - ball wafer level chip scale package (wlcsp ) (cb -6- 4) d imensions shown in millimeters ordering guide model 1 temperature range output voltage (v) package description package option 2 branding adp2121acbz - 1.8-r7 ?40 c to +85 c 1.8 6- ball wafer level chip scale package [wlcsp] cb -6-4 l92 adp2121acbz - 1.82r7 ? 40 c to +85 c 1.82 6- ball wafer level chip scale package [wlcsp] cb -6-4 l 7n adp2121acbz - 1.85r7 ?40 c to +85 c 1.85 6- ball wafer level chip scale package [wlcsp] cb -6-4 l94 adp2121acbz -1 875r7 ?40 c to +85 c 1.875 6- ball wafer level chip scale packa ge [wlcsp] cb -6-4 l95 adp2121acbz - 2.3-r7 ?40 c to +85 c 2.3 6- ball wafer level chip scale package [wlcsp] cb -6-4 l9g adp2121 - 1.8- evalz 1.8 evaluation board for 1.8 v adp2121 - 1.82- evalz 1.82 evaluation board for 1.82 v adp2121 - 1.85- evalz 1.85 evaluation board for 1.85 v adp2121 - 1.875evalz 1.875 evaluation board for 1.875 v adp2121 - 2.3- evalz 2.3 evaluation board for 2.3 v 1 z = rohs compliant part. 2 halide free. ? 2009 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07407 -0- 1/11(b)

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